The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2019

Filed:

Jul. 15, 2016
Applicant:

Sony Corporation, Tokyo, JP;

Inventors:

Mitsuru Asano, Kanagawa, JP;

Seiichiro Jinta, Kanagawa, JP;

Masatsugu Tomida, Kanagawa, JP;

Hiroshi Fujimura, Aichi, JP;

Assignee:

Sony Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/136 (2006.01); H01L 27/32 (2006.01); G09G 3/3233 (2016.01); H01L 27/12 (2006.01); G09G 3/3258 (2016.01);
U.S. Cl.
CPC ...
H01L 27/3262 (2013.01); G09G 3/3233 (2013.01); G09G 3/3258 (2013.01); H01L 27/1214 (2013.01); H01L 27/326 (2013.01); H01L 27/3265 (2013.01); H01L 27/3276 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0809 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/0262 (2013.01); H01L 27/3269 (2013.01);
Abstract

Herein disclosed a display apparatus including: a pixel array having a matrix of pixel circuits each including respective electrooptical elements for determining a display brightness level and respective drive circuits for driving the electrooptical elements; wherein adjacent two of the pixel circuits are paired with each other, and each of the drive circuits of the adjacent two pixel circuits includes at least one transistor having a low-concentration source/drain region or an offset region of an offset gate structure, the electrooptical elements and the drive circuits of the adjacent two pixel circuits being laid out such that a line interconnecting a drain region and a source region of the at least one transistor extends parallel to a direction of pixel columns of the pixel circuits of the pixel array.


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