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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10504960 B1

PDFFull Text
Date of Patent:
Dec. 10, 2019

Filed:

Mar. 13, 2018

Semiconductor memory devices

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Kichul Park, Hwaseong-si, KR;

Ki-Woong Kim, Songbuk-gu, KR;

Hansol Seok, Suwon-si, KR;

Byoungho Kwon, Hwaseong-si, KR;

Boun Yoon, Seoul, KR;

Assignee:

Samsung Electronics Co., Ltd., Gyeonggi-do, KR;

Attorney:

Harness, Dickey and Pierce, P.L.C.

Primary Examiner:

Charles D Garber

Assistant Examiner:

Alia Sabur

Int. Cl.
CPC ...
H01L 27/22 (2006.01); H01L 43/08 (2006.01); H01L 43/02 (2006.01); H01F 10/32 (2006.01); H01L 23/532 (2006.01); H01L 23/528 (2006.01); G11C 11/16 (2006.01); H01L 43/12 (2006.01); H01L 21/768 (2006.01); H01L 21/027 (2006.01); H01L 21/3213 (2006.01); H01L 23/522 (2006.01); H01L 21/321 (2006.01);
U.S. Cl.
CPC ...
H01L 27/228 (2013.01); G11C 11/161 (2013.01); H01F 10/3254 (2013.01); H01F 10/3286 (2013.01); H01L 21/0274 (2013.01); H01L 21/32136 (2013.01); H01L 21/7685 (2013.01); H01L 21/76802 (2013.01); H01L 21/76843 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/53266 (2013.01); H01L 43/02 (2013.01); H01L 43/08 (2013.01); H01L 43/12 (2013.01); H01F 10/3272 (2013.01); H01L 21/3212 (2013.01); H01L 21/7684 (2013.01);
Abstract

A semiconductor memory device may include a selection transistor on a semiconductor substrate, an interlayered insulating layer covering the selection transistor, a lower contact plug coupled to a drain region of the selection transistor and configured to penetrate the interlayered insulating layer, and a magnetic tunnel junction pattern coupled to the lower contact plug. The lower contact plug may include a metal pattern and a capping metal pattern in contact with a top surface of the metal pattern. The capping metal pattern may include a top surface having a surface roughness that is smaller than a surface roughness of the top surface of the metal pattern. The magnetic tunnel junction pattern may include bottom and top electrodes, a lower magnetic layer and an upper magnetic layer between the top and bottom electrodes, and a tunnel barrier layer between the lower magnetic layer and the upper magnetic layer.

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