The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2019

Filed:

Nov. 23, 2015
Applicant:

Institute of Microelectronics, Chinese Academy of Sciences, Beijing, CN;

Inventors:

Zongliang Huo, Beijing, CN;

Tianchun Ye, Beijing, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 21/308 (2006.01); H01L 21/306 (2006.01); H01L 21/762 (2006.01); H01L 21/02 (2006.01); H01L 21/027 (2006.01); H01L 21/311 (2006.01); H01L 29/10 (2006.01); H01L 21/28 (2006.01); H01L 29/792 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/0274 (2013.01); H01L 21/02164 (2013.01); H01L 21/02532 (2013.01); H01L 21/308 (2013.01); H01L 21/30604 (2013.01); H01L 21/31111 (2013.01); H01L 21/762 (2013.01); H01L 21/76224 (2013.01); H01L 29/1037 (2013.01); H01L 29/40117 (2019.08); H01L 29/7926 (2013.01); H01L 21/02592 (2013.01); H01L 21/02595 (2013.01); H01L 21/02636 (2013.01); H01L 29/66545 (2013.01); H01L 29/66833 (2013.01);
Abstract

A three-dimensional memory device and method of manufacturing the same, an isolation structure is embedded between the common source region and the substrate thereunder, which can inhibit the undesired diffusion of impurities during the implantation of the common source region, avoiding operation failure due to excessive diffusion of impurities. In programming and reading states of the three-dimensional memory device, electrons flow from the common source region to bit line; while in erase states, holes are injected from the substrate. Due to the isolation structure, the three-dimensional memory device achieves spatial separation of electrons from holes required for programming/erasing, improving the erasing efficiency and the integration as well.


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