The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 10, 2019
Filed:
Jun. 08, 2016
Fujian Cas-ceramic Optoelectronics Technology Co., Ltd, Fuzhou, Fujian, CN;
Shanghui Ye, Fujian, CN;
Jieqin Zhang, Fujian, CN;
Maochun Hong, Fujian, CN;
Wenxiong Lin, Fujian, CN;
Wang Guo, Fujian, CN;
Yunfeng Zhang, Fujian, CN;
FUJIAN CAS-CERAMIC OPTOELECTRONICS TECHNOLOGY CO., LTD, Fuzhou, Fujian, CN;
Abstract
A die-bonding substrate has a substrate, and a conductive line layer and a chip array provided on the substrate. The conductive line layer includes a chip welding wire region and an external electrode region connected with each other. The chip welding wire region is composed of multiple conductive lines, wherein the central conductive line located in the central position of the chip welding wire region is a straight line section. The conductive lines arranged at both sides of the central conductive line are straight line sections at both ends, and arc sections curved outwards in the middle, so that the entire chip welding wire region forms a circular area. The array chips are arranged inside the circular area, and are electrically connected with the conductive lines arranged at both sides. The entire chip welding wire region can also form a rectangular area.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile