The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2019

Filed:

Aug. 07, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventor:

Jeong-Kyu Ha, Hwaseong-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49838 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/563 (2013.01); H01L 23/3185 (2013.01); H01L 23/4985 (2013.01); H01L 23/49822 (2013.01); H01L 24/16 (2013.01); H01L 2224/16227 (2013.01);
Abstract

A semiconductor package includes a substrate having a top surface on which a semiconductor chip is mounted and a bottom surface opposite the top surface, an upper metal pattern including an upper connection region to which an external electrical device is connected and a chip connection region to which the semiconductor chip is connected, a lower metal pattern including a lower connection region to which other external electrical device is connected, and an intermediate metal pattern electrically connecting the upper and lower metal patterns. The upper metal pattern provides at least three groups of inner leads. The lower metal pattern provides at least three groups of outer leads. A module, such as that of a display device, may include the semiconductor package.


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