The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2019

Filed:

Oct. 14, 2016
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

James Edward Myers, Bottisham, GB;

David William Howard, Cambridge, GB;

John Philip Biggs, Cambridge, GB;

Assignee:

ARM Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 14/00 (2006.01); G11C 17/14 (2006.01); H01L 27/12 (2006.01); G11C 17/18 (2006.01); G11C 11/40 (2006.01); G11C 17/12 (2006.01);
U.S. Cl.
CPC ...
G11C 11/005 (2013.01); G11C 14/0054 (2013.01); G11C 17/14 (2013.01); G11C 11/40 (2013.01); G11C 17/12 (2013.01); G11C 17/18 (2013.01); H01L 27/12 (2013.01);
Abstract

A circuit comprises an array of programmable memory elements fabricated on a substrate, each memory element having one or more processable regions which, when processed by an external process in which a material is applied to at least partially cover one or more of the regions, are configured to program that memory element to one of multiple states; a first set of control lines connected to the array of memory elements, by which the contents of each individual memory element are capable of being accessed by control signals applied to a respective combination of at least two control lines in the first set of control lines; and an array of second circuit elements, different to the memory elements, each connected to a control line of the first set of control lines and to another control line of a second set of control lines, different to the first set of control lines, so as to provide access to second circuit elements in the array.


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