The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2019

Filed:

Dec. 21, 2017
Applicant:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Inventors:

Guanhao Shen, Austin, TX (US);

Ravindra N. Bhargava, Austin, TX (US);

James Raymond Magro, Austin, TX (US);

Kedarnath Balakrishnan, Whitefield, IN;

Jing Wang, Austin, TX (US);

Assignee:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G11C 11/406 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1636 (2013.01); G06F 13/1642 (2013.01); G06F 13/4234 (2013.01); G11C 11/40603 (2013.01);
Abstract

Systems, apparatuses, and methods for performing efficient memory accesses in a computing system are disclosed. In various embodiments, a computing system includes computing resources and a memory controller coupled to a memory device. The memory controller determines a memory request targets a given rank of multiple ranks. The memory controller determines a predicted latency for the given rank as an amount of time the pending queue in the memory controller for storing outstanding memory requests does not store any memory requests targeting the given rank. The memory controller determines the total bank latency as an amount of time for refreshing a number of banks which have not yet been refreshed in the given rank with per-bank refresh operations. If there are no pending requests targeting the given rank, each of the predicted latency and the total bank latency is used to select between per-bank and all-bank refresh operations.


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