The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2019

Filed:

May. 20, 2015
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Mattheus Cornelis Antonius Adrianus Heddes, Raleigh, NC (US);

Natarajan Vaidhyanathan, Carrboro, NC (US);

Colin Beaton Verrilli, Apex, NC (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/0811 (2016.01); G06F 12/1081 (2016.01); G06F 12/0817 (2016.01); G06F 12/0831 (2016.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1081 (2013.01); G06F 12/023 (2013.01); G06F 12/0811 (2013.01); G06F 12/0817 (2013.01); G06F 12/0833 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/2532 (2013.01); G06F 2212/401 (2013.01); G06F 2212/452 (2013.01); G06F 2212/62 (2013.01); G06F 2212/621 (2013.01); G06F 2212/622 (2013.01); Y02D 10/13 (2018.01);
Abstract

Providing memory bandwidth compression using compressed memory controllers (CMCs) in a central processing unit (CPU)-based system is disclosed. In this regard, in some aspects, a CMC is configured to receive a memory read request to a physical address in a system memory, and read a compression indicator (CI) for the physical address from a master directory and/or from error correcting code (ECC) bits of the physical address. Based on the CI, the CMC determines a number of memory blocks to be read for the memory read request, and reads the determined number of memory blocks. In some aspects, a CMC is configured to receive a memory write request to a physical address in the system memory, and generate a CI for write data based on a compression pattern of the write data. The CMC updates the master directory and/or the ECC bits of the physical address with the generated CI.


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