The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2019

Filed:

Jun. 21, 2017
Applicant:

Emc Ip Holding Company Llc, Hopkinton, MA (US);

Inventors:

Mark Himelstein, Emerald Hills, CA (US);

Bruce Wilford, Los Altos, CA (US);

Richard Van Gaasbeck, Mountain View, CA (US);

Todd Wilde, Mountain View, CA (US);

Rick Carlson, Pacific Palisades, CA (US);

Vikram Venkataraghavan, Saratoga, CA (US);

Vishwas Durai, Los Altos, CA (US);

Blair Barnett, Mountain View, CA (US);

Kevin Rowett, Cupertino, CA (US);

Assignee:

EMC IP Holdings Company LLC, Hopkinton, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0619 (2013.01); G06F 3/065 (2013.01); G06F 3/067 (2013.01); G06F 3/0688 (2013.01); G06F 13/4282 (2013.01); G06F 2213/0026 (2013.01);
Abstract

According to one embodiment, a data processing system includes a plurality of central processing unit (CPU) subsystems, each CPU subsystem having a plurality of CPUs and a plurality of memory controllers, each memory controller corresponding to one of the CPUs, a plurality of memory complexes, each memory complex being associated with one of the CPU subsystems, wherein each memory complex comprises one or more branches, a plurality of memory leaves to store data, wherein each of the branches is coupled to one or more of the memory leaves and to provide access to the data stored in the memory leaves, and a replication interface to automatically replicate data received from one of the CPU subsystems to another one of the memory complexes, wherein the received data is to be stored in one of the memory leaves.


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