The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 10, 2019
Filed:
Nov. 10, 2017
International Business Machines Corporation, Armonk, NY (US);
Victor N. Kravets, White Plains, NY (US);
Haoxing Ren, Austin, TX (US);
Mary P. Kusko, Hopewell Junction, NY (US);
Spencer K. Millican, Rochester, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A system and method for using unreachable states of a circuit design in a testing mode to increase random testability of a random resistant logic circuit. Control-improving logic circuitry is integrated into a logic circuit design to improve its testability and will not affect behavior of the design in its functional mode (by remaining 'inactive' in the functional mode of the integrated circuit). The control-improving logic circuitry is automatically activated in testing mode. The control improving logic circuit is generated selectively for random resistant logic circuit regions that exhibit limited controllability in the functional mode and improves controllability of random resistant logic in the testing mode. The improved controllability results from activating test circuitry in the states that are not reachable during normal functionality. The utilization of unreachable states of a design renders unnecessary use of an explicit test enable signal, and provides for more compact implementation of test circuitry.