The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2019

Filed:

Nov. 01, 2018
Applicant:

Himax Imaging Limited, Tainan, TW;

Inventors:

Hack Soo Oh, Tainan, TW;

Youngchul Sohn, Tainan, TW;

Kwangoh Kim, Tainan, TW;

Assignee:

Himax Imaging Limited, Tainan, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04N 5/365 (2011.01); H04N 5/374 (2011.01); H04N 5/378 (2011.01);
U.S. Cl.
CPC ...
H04N 5/3658 (2013.01); H04N 5/374 (2013.01); H04N 5/378 (2013.01);
Abstract

A digital double-sampling (DDS) circuit includes a comparator with input nodes respectively connected to a ramp voltage and an image output node of a pixel circuit via a capacitor; a reset switch connected between the input nodes for resetting the capacitor; an analog-to-digital converter (ADC) coupled to receive a comparison output of the comparator, the ADC including a counter that counts while the ramp voltage is ramping, thereby generating a reset-ADC value in a reset phase and generating a signal-ADC value in a signal phase; a subtractor that subtracts the reset-ADC value from the signal-ADC value, thereby resulting in a difference value representing a sampled output; and a clamp circuit that generates a clamp voltage at the image output node. In the reset phase, the clamp circuit is disabled after the capacitor finishes resetting but before the ramp voltage begins ramping.


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