The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2019

Filed:

Nov. 21, 2017
Applicant:

Vertiv Tech Co., Ltd., Shenzhen, Guangdong, CN;

Inventors:

Junke Wu, Guangdong, CN;

Jianning Yang, Guangdong, CN;

Assignee:

Vertiv Tech Co., Ltd., Shenzhen, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M 7/483 (2007.01); H02M 7/537 (2006.01); H02M 7/487 (2007.01);
U.S. Cl.
CPC ...
H02M 7/483 (2013.01); H02M 7/487 (2013.01); H02M 7/537 (2013.01);
Abstract

Provided is a multi-level inverter, which includes a first bus capacitor, a second bus capacitor, a third bus capacitor, a fourth bus capacitor, a seventh switch unit, an eighth switch unit, an inverter circuit and a filtering circuit. The first bus capacitor, the second bus capacitor, the third bus capacitor and the fourth bus capacitor are connected between a positive direct current bus and a negative direct current bus in series, and a series point between the second bus capacitor and the third bus capacitor is grounded. The switch transistor of the anti-parallel diode having small on-state resistance is used in the multi-level inverter, thereby reducing power loss of the switch unit in the multi-level inverter and reducing power consumption of the circuit.


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