The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2019

Filed:

Mar. 27, 2018
Applicant:

Technion Research & Development Foundation Limited, Haifa, IL;

Inventors:

Nir Tessler, Zichron Jacob, IL;

Ariel Jacques Ben Sasson, Haifa, IL;

Michael Greenman, Haifa, IL;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 29/417 (2006.01); H01L 51/05 (2006.01); H01L 51/10 (2006.01); H01L 29/08 (2006.01); H01L 29/45 (2006.01); H01L 29/78 (2006.01); H01L 29/861 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41741 (2013.01); H01L 29/0847 (2013.01); H01L 29/456 (2013.01); H01L 29/7827 (2013.01); H01L 29/861 (2013.01); H01L 51/057 (2013.01); H01L 51/105 (2013.01);
Abstract

A transistor structure is configured as a vertical type transistor. The transistor structure has a patterned electrode located between a gate electrode and a channel region of the transistor structure. The patterned electrode has one or more regions of discontinuity of the electrode. The patterned source electrode has at least two layers having at least a first and second barriers for injection of charge carriers into the channel region. The patterned electrode is configured such that a second layer having a second, higher, barrier for injection of charge carriers is configured to provide a physical barrier for flow of charge carriers from the electrode into the channel region.


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