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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10497694 B1

PDFFull Text
Date of Patent:
Dec. 03, 2019

Filed:

Apr. 27, 2018

Power semiconductor devices and a method for forming a power semiconductor device

Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Joachim Mahler, Regensburg, DE;

Guenther Kolmeder, Altdorf, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:

Murphy, Bilak & Homiller, PLLC

Primary Examiner:

Igwe U Anya

Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 23/367 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 29/06 (2006.01); H01L 21/8234 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0211 (2013.01); H01L 23/367 (2013.01); H01L 23/49513 (2013.01); H01L 23/49562 (2013.01); H01L 24/32 (2013.01); H01L 24/49 (2013.01); H01L 24/73 (2013.01); H01L 27/0248 (2013.01); H01L 29/0696 (2013.01); H01L 29/66681 (2013.01); H01L 29/7823 (2013.01); H01L 29/7826 (2013.01); H01L 21/823418 (2013.01); H01L 21/823475 (2013.01); H01L 27/0922 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/49175 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/13055 (2013.01);
Abstract

A power semiconductor device includes a power transistor arranged in a power device region of a semiconductor substrate. The power semiconductor device further includes a first circuit arranged in a first circuit region of the semiconductor substrate. The power semiconductor device further includes a second circuit arranged in a second circuit region of the semiconductor substrate. The first circuit region is arranged at a first edge of the semiconductor substrate. The second circuit region is arranged at a second edge of the semiconductor substrate. The power device region is arranged between the first circuit region and the second circuit region.

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