The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 03, 2019
Filed:
Jan. 11, 2017
Applicant:
Apple Inc., Cupertino, CA (US);
Inventors:
Imran Hashim, Saratoga, CA (US);
Vaibhav D. Patel, San Jose, CA (US);
Hsin-Hua Hu, Los Altos, CA (US);
Kapil V. Sakariya, Los Altos, CA (US);
Ralph E. Kauffman, San Jose, CA (US);
Assignee:
Apple Inc., Cupertino, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/075 (2006.01); H01L 33/62 (2010.01); H01L 33/44 (2010.01); H01L 33/48 (2010.01); H01L 25/16 (2006.01); H01L 33/52 (2010.01);
U.S. Cl.
CPC ...
H01L 25/0753 (2013.01); H01L 33/44 (2013.01); H01L 33/486 (2013.01); H01L 33/62 (2013.01); H01L 25/167 (2013.01); H01L 33/52 (2013.01); H01L 2933/0025 (2013.01); H01L 2933/0066 (2013.01);
Abstract
Display integration schemes are described for passivating LEDs and providing conductive terminal connections. In accordance with embodiments, a sidewall passivation layer is formed around the LEDs. The sidewall passivation layer may or may not be contained within a well structure. A top electrode layer is formed to electrically connect the LEDs to conductive terminal routing.