The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2019

Filed:

Apr. 05, 2018
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventor:

Doug Weiser, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 22/32 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 28/20 (2013.01);
Abstract

An electronic device, e.g. an integrated circuit, includes one or more test modules each having first and second pairs of contact pads arranged along a first axis, and a third pair of contact pads arranged along a second axis parallel to the first axis. A first connection bus connects contact pads in the first pair, a second connection bus connects contact pads in the second pair, and a third connection bus connects contact pads of the third pair. A first device under test (DUT) is connected between the first connection bus and the third connection bus, and a second DUT is connected between the second connection bus and the third connection bus.


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Weiser, Doug. (2019). High density wafer level test module (U.S. Patent No. 10497630). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10497630

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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