The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2019

Filed:

Jun. 26, 2017
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;

Inventors:

Kyung-Min Kang, Hwaseong-si, KR;

Dongku Kang, Seongnam-si, KR;

Kwang Won Kim, Seoul, KR;

HyunJin Kim, Hwaseong-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/20 (2006.01); G06F 13/38 (2006.01); G06F 3/06 (2006.01); G11C 29/00 (2006.01); G06F 11/10 (2006.01); G11C 16/12 (2006.01); G11C 16/16 (2006.01); G11C 16/32 (2006.01); G11C 16/34 (2006.01); G11C 5/02 (2006.01); G11C 7/10 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01);
U.S. Cl.
CPC ...
G11C 29/789 (2013.01); G06F 11/1068 (2013.01); G06F 11/1072 (2013.01); G11C 5/025 (2013.01); G11C 7/1006 (2013.01); G11C 7/1009 (2013.01); G11C 16/10 (2013.01); G11C 16/12 (2013.01); G11C 16/16 (2013.01); G11C 16/26 (2013.01); G11C 16/32 (2013.01); G11C 16/344 (2013.01); G11C 2211/5642 (2013.01);
Abstract

A nonvolatile memory device includes a memory cell array including first to fourth planes, a page buffer circuit that includes first to fourth page buffer units connected with the first to fourth planes, respectively, an input/output circuit that includes a first input/output unit connected with the first to fourth page buffer units and a second input/output unit connected with the second and fourth page buffer units, and control logic that controls the input/output circuit to output first data from one of the first to fourth page buffer units through the first input/output unit in a first read mode and output second data from one of the first and third page buffer units through the first input/output unit and third data from one of the second and fourth page buffer units through the second input/output unit in a second read mode.


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