The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2019

Filed:

Nov. 15, 2018
Applicant:

Hewlett Packard Enterprise Development Lp, Houston, TX (US);

Inventors:

Suhas Kumar, Palo Alto, CA (US);

Rui Liu, Palo Alto, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); G06F 9/30 (2018.01); H01L 27/24 (2006.01); G06F 17/16 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0069 (2013.01); G06F 9/30014 (2013.01); G06F 17/16 (2013.01); G11C 13/004 (2013.01); H01L 27/2463 (2013.01); G11C 2013/0045 (2013.01);
Abstract

In example implementations, a memory cell is provided. The memory cell includes a plurality of row lines and a plurality of column lines. The plurality of row lines and the plurality of column lines intersect to form a 2×2 array. The memory cell may include a plurality of memristors. A memristor is coupled to each unique combination of a row line and a column line in the 2×2 array. An input line is coupled to a first row of memristors. An invert is coupled to the input line. An inverted input line from the inverter is coupled to the second row of memristors.


Find Patent Forward Citations

Kumar, Suhas. (2019). Memristor arrays in crossbars (U.S. Patent No. 10497442). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10497442

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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