The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2019

Filed:

Nov. 14, 2017
Applicant:

Lg Display Co., Ltd., Seoul, KR;

Inventors:

Seok Noh, Chungcheongnam-do, KR;

Injune Kim, Seoul, KR;

Kimin Son, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 19/00 (2006.01); G09G 3/36 (2006.01); G09G 3/3266 (2016.01); G11C 19/28 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3696 (2013.01); G09G 3/3266 (2013.01); G09G 3/3677 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0871 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0219 (2013.01); G09G 2320/043 (2013.01); G11C 19/28 (2013.01);
Abstract

A display device comprises: a pixel array including pixels connected to gate lines; a gate driver that sequentially supplies scan signals to the gate lines by using a plurality of stages connected in cascade; and a driving voltage generator that supplies first and second driving voltages to the gate driver and inverts the first and second driving voltages of opposite phases at given intervals, wherein an nth stage (n is a natural number), among the stages of the gate driver, comprises: a start controller that charges a Qnode in a period when an (n−1)th scan signal and a first clock signal are synchronized, and charges a QB node in a period when an (n−1)th carry signal, opposite in phase to the (n−1)th scan signal, and the first clock signal are synchronized; a first node controller that charges a Qnode or a QB node in response to a voltage at the Qnode; a first output control transistor that outputs an nth scan signal through a Q node in response to a voltage at the Qnode; and a second output control transistor that charges the Q node with the second driving voltage in response to a voltage at the QB node.


Find Patent Forward Citations

Loading…