The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2019

Filed:

Nov. 11, 2016
Applicant:

Total Phase, Inc., Santa Clara, CA (US);

Inventors:

Thomas P. Holden, Sunnyvale, CA (US);

Kumaran Santhanam, Sunnyvale, CA (US);

Assignee:

Total Phase, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/445 (2018.01); G06F 9/455 (2018.01); G11C 14/00 (2006.01); G06F 9/4401 (2018.01); G11C 11/00 (2006.01); G06F 13/38 (2006.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G06F 9/455 (2013.01); G06F 9/4411 (2013.01); G06F 12/0292 (2013.01); G06F 13/387 (2013.01); G11C 11/005 (2013.01); G11C 14/0009 (2013.01); G11C 14/0054 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/1044 (2013.01);
Abstract

A digital logic device is disclosed that includes registers, SRAM, DRAM, and a processor configured to store in the registers an initial portion of a first response data to a command, and store in the SRAM the first response data. The processor is further configured to store in a lookup table the memory location and size of the first response data in the SRAM, store in the DRAM additional response data, and store in the lookup table the memory location and size of the additional response data in the DRAM. The processor is configured to receive the command from a host device, retrieve the first response data from the registers or the SRAM, and send the first response data to the host. If the command includes additional response data, the processor is configured to concurrently retrieve the additional response data from DRAM and send the additional response data to the host.


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