The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2019

Filed:

Jun. 21, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Sundeep Chadha, Austin, TX (US);

Robert A. Cordes, Austin, TX (US);

David A. Hrusecky, Cedar Park, TX (US);

Hung Q. Le, Austin, TX (US);

Jentje Leenstra, Bondorf, DE;

Dung Q. Nguyen, Austin, TX (US);

Brian W. Thompto, Austin, TX (US);

Albert J. Van Norstrand, Jr., Round Rock, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0842 (2016.01); G06F 9/30 (2018.01); G06F 12/0813 (2016.01); G06F 12/0875 (2016.01); G06F 12/0862 (2016.01); G06F 13/16 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 9/30047 (2013.01); G06F 12/0813 (2013.01); G06F 12/0842 (2013.01); G06F 12/0862 (2013.01); G06F 12/0875 (2013.01); G06F 13/1668 (2013.01); G06F 13/4282 (2013.01); G06F 2212/283 (2013.01); G06F 2212/452 (2013.01); G06F 2212/602 (2013.01); G06F 2212/62 (2013.01); G06F 2213/0042 (2013.01);
Abstract

Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.


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