The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2019

Filed:

Jun. 07, 2018
Applicant:

Seiko Epson Corporation, Tokyo, JP;

Inventor:

Hitoya Nagasawa, Matsumoto, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1362 (2006.01); G02F 1/1335 (2006.01); G02F 1/133 (2006.01); G02F 1/1343 (2006.01); G02F 1/1345 (2006.01); H01L 29/786 (2006.01); G02F 1/1368 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
G02F 1/136286 (2013.01); G02F 1/1343 (2013.01); G02F 1/13306 (2013.01); G02F 1/13454 (2013.01); G02F 1/133512 (2013.01); H01L 27/1222 (2013.01); H01L 29/78633 (2013.01); H01L 29/78675 (2013.01); G02F 1/136209 (2013.01); G02F 2001/13685 (2013.01); G02F 2201/123 (2013.01);
Abstract

An electro-optical device (e.g., a liquid crystal device) includes a data line connected to a switching element provided for each pixel, a sampling transistor that has a gate supplied with a selection signal, a source supplied with an image signal, and a drain connected to the data line, and a monitoring transistor. A gate of the monitoring transistor is supplied with an input signal. A delay signal indicating a delay amount of the selection signal is sent out from a drain of the monitoring transistor. The sampling transistor includes a plurality of transistors connected in parallel to each other along the data line. The monitoring transistor includes one transistor along the data line.


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