The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2019

Filed:

Jun. 22, 2018
Applicant:

Samsung Display Co., Ltd., Yongin-si, Gyeonggi-do, KR;

Inventors:

Young Gu Kim, Yongin-si, KR;

Taek Joon Lee, Hwaseong-si, KR;

Hye Lim Jang, Hwaseong-si, KR;

Baek Kyun Jeon, Yongin-si, KR;

Jin-Soo Jung, Hwaseong-si, KR;

Young Bong Cho, Seongnam-si, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1335 (2006.01); H01L 27/32 (2006.01); G02F 1/1368 (2006.01); G02F 1/1362 (2006.01);
U.S. Cl.
CPC ...
G02F 1/133617 (2013.01); G02F 1/1368 (2013.01); H01L 27/322 (2013.01); H01L 27/3244 (2013.01); G02F 2001/133614 (2013.01); G02F 2001/136222 (2013.01); G02F 2202/36 (2013.01); G02F 2203/023 (2013.01);
Abstract

A display device according to an exemplary embodiment includes: a thin film transistor array panel; and a color conversion display panel overlapping the thin film transistor array panel, the color conversion display panel including: a substrate; a color conversion layer positioned between the substrate and the thin film transistor array panel and including a semiconductor nanocrystal; a transparent layer positioned between the substrate and the thin film transistor array panel; and at least one of a first buffer layer positioned between the color conversion layer and the substrate and between the transparent layer and the substrate, and a second buffer layer positioned between the color conversion layer and the thin film transistor array panel and between the transparent layer and the thin film transistor array panel, and at least one of the first buffer layer and the second buffer layer includes a porous layer.


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