The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2019

Filed:

May. 01, 2017
Applicant:

Kuraray Co., Ltd., Kurashiki-shi, JP;

Inventors:

Takeshi Takahashi, Kamisu, JP;

Takahiro Nakashima, Kamisu, JP;

Minoru Onodera, Saijo, JP;

Tetsuya Hara, Kurashiki, JP;

Assignee:

KURARAY CO., LTD., Kurashiki-shi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01K 3/22 (2006.01); H05K 3/46 (2006.01); H05K 1/03 (2006.01); H05K 3/10 (2006.01); B32B 15/08 (2006.01); B32B 38/00 (2006.01); B29C 65/00 (2006.01); B29C 65/02 (2006.01); B29L 31/34 (2006.01);
U.S. Cl.
CPC ...
H05K 3/4632 (2013.01); B32B 15/08 (2013.01); B32B 38/0036 (2013.01); H05K 1/0313 (2013.01); H05K 1/0393 (2013.01); H05K 3/10 (2013.01); H05K 3/4635 (2013.01); B29C 65/02 (2013.01); B29C 66/034 (2013.01); B29C 66/1122 (2013.01); B29C 66/45 (2013.01); B29C 66/7352 (2013.01); B29C 66/7392 (2013.01); B29C 66/73921 (2013.01); B29C 66/742 (2013.01); B29C 66/91411 (2013.01); B29C 66/91445 (2013.01); B29C 66/91933 (2013.01); B29L 2031/3425 (2013.01); H05K 2201/0129 (2013.01); H05K 2201/0141 (2013.01); H05K 2201/0355 (2013.01); H05K 2203/0278 (2013.01); H05K 2203/111 (2013.01); H05K 2203/1178 (2013.01); H05K 2203/1194 (2013.01);
Abstract

Provided are circuit board excellent in interlayer adhesion and solder heat resistance, and production method thereof. The circuit board is produced by a method including: preparing a plurality of at least one kind of thermoplastic liquid crystal polymer (TLCP) films, forming a conductor layer on one side or both sides of a film in at least one of the films to obtain a unit circuit board, laminating the films containing the unit circuit board to obtain a stacked material, conducting thermo-compression-bonding of the stacked material under pressurization to a first temperature giving an interlayer adhesion to integrate the stacked material, carrying out structure-controlling thermal treatment by heating the integrated stacked material at a second temperature which is lower than the first temperature and is lower than a melting point of a TLCP having a lowest melting point out of the plurality of TLCP films.


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