The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2019

Filed:

Oct. 01, 2018
Applicants:

Ahmed Mohamed Ibrahim Medra, Kanata, CA;

Hossein Najafi, Kanata, CA;

Zhuhong Zhang, Ottawa, CA;

Inventors:

Ahmed Mohamed Ibrahim Medra, Kanata, CA;

Hossein Najafi, Kanata, CA;

Zhuhong Zhang, Ottawa, CA;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 1/16 (2006.01); H04L 25/03 (2006.01); H04L 1/00 (2006.01);
U.S. Cl.
CPC ...
H04L 25/03057 (2013.01); H04B 1/16 (2013.01); H04L 1/0054 (2013.01);
Abstract

A symbol detection and forward error correction (FEC) decoding system and method are disclosed that aim to increase decoding performance and maintain an acceptable level of complexity. In one embodiment, the method includes performing detection and decoding over a plurality of iterations. During the first iteration: a first equalizer structure processes a received signal, and a FEC decoder performs decoding on an input obtained from the output of the first equalizer structure. During the other iterations: an iterative equalizer structure processes both (i) the received signal and (ii) an input obtained from an output of the FEC decoder from a previous iteration of the detection and decoding, in order to generate an output of the iterative equalizer structure, and the FEC decoder performs FEC decoding on an input obtained from the output of the iterative equalizer structure.


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