The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2019

Filed:

Feb. 20, 2019
Applicants:

Stichting Imec Nederland, Eindhoven, NL;

Technische Universiteit Delft, Delft, NL;

Inventors:

Ming Ding, Eindhoven, NL;

Zhihao Zhou, Eindhoven, NL;

Yao-Hong Liu, Eindhoven, NL;

Fabio Sebastiano, Delft, NL;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01); H03L 7/093 (2006.01); H03L 7/099 (2006.01);
U.S. Cl.
CPC ...
H03L 7/093 (2013.01); H03L 7/099 (2013.01);
Abstract

The present disclosure describes systems and methods to provide a digital wakeup timer with reduced size and lower power. An example system or apparatus includes a wakeup timer employing a digital-intensive frequency-locked loop (DFLL) architecture to fully utilize the advantages of advanced CMOS processes. Such a system includes a bang-bang frequency detector, a digital loop filter, a digitally-controlled oscillator (DCO), and a multi-phase clock generator. An output of the bang-bang frequency detector is provided to an input of the digital loop filter. An output of the digital loop filter is provided to the DCO. An output of the DCO includes information indicative of an output frequency. The multi-phase clock generator provides respective clock signals based on the output frequency to the bang-bang frequency detector, the digital loop filter, and the DCO.


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