The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2019

Filed:

Sep. 20, 2017
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Vivekanandan Venugopal, San Jose, CA (US);

Michael R Seningen, Austin, TX (US);

Ajay Bhatia, Saratoga, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/037 (2006.01); H03K 3/012 (2006.01); H03K 3/3562 (2006.01);
U.S. Cl.
CPC ...
H03K 3/0372 (2013.01); H03K 3/012 (2013.01); H03K 3/35625 (2013.01);
Abstract

An electronic circuit is disclosed. A first flip-flop is coupled to receive a clock signal from clock gating circuit. The first flip-flop includes an input circuit having a data input, a master-slave latch, and an output circuit. Responsive to an edge of the clock signal, the master-slave latch may latch a logic value of a signal received on the data input. The output circuit is coupled to the master-slave latch, and provides a logic output signal corresponding to the logic value latched by the master-slave latch. The clock gating circuit may provide one or more inversions of the clock signal which it receives. The flip-flop provides no inversions of the clock signal.


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