The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2019

Filed:

Oct. 19, 2016
Applicant:

Lumileds Holding B.v., Schiphol, NL;

Inventors:

Wen Yu, Pleasanton, CA (US);

Oleg B. Shchekin, San Francisco, CA (US);

Franklin Wall, Vacaville, CA (US);

Kuochou Tai, Fremont, CA (US);

Mohiuddin Mala, San Jose, CA (US);

Robert Zona, San Jose, CA (US);

Jeffrey Kmetec, Palo Alto, CA (US);

Alexander Nickel, Santa Clara, CA (US);

Assignee:

Lumileds Holding B.V., Schiphol, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/00 (2010.01); H01L 33/62 (2010.01); H01L 23/00 (2006.01); H01L 27/15 (2006.01); H01L 33/38 (2010.01); H01L 25/075 (2006.01);
U.S. Cl.
CPC ...
H01L 33/62 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 25/0753 (2013.01); H01L 27/153 (2013.01); H01L 33/38 (2013.01); H01L 2224/05013 (2013.01); H01L 2924/12041 (2013.01);
Abstract

Light emitting die () comprising a plurality of light emitting elements (310A, 310B), each having a pair of bond pads (NPand NP), wherein at least two diagonally opposite bond pads of adjacent light emitting elements on a die have their facing corners truncated () to enable a direct diagonal coupling of a complementary pair of diagonally opposite bond pads when the die is monted on a substrate on which an interconnection pattern is formed. By enabling diagonal as well as lateral coupling of the bond pads of multiple light emitting elements of a die, the multiple light emitting elements may be arranged in a variety of series and/or parallel configurations, thereby facilitating the use of the same die at different nominal operating voltages with a single interconnect layer on the substrate upon which the die is mounted.


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