The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2019

Filed:

May. 30, 2018
Applicant:

Qorvo Us, Inc., Greensboro, NC (US);

Inventors:

Julio C. Costa, Oak Ridge, NC (US);

Merrill Albert Hatcher, Jr., Greensboro, NC (US);

Peter V. Wright, Portland, OR (US);

Jon Chadwick, Greensboro, NC (US);

Assignee:

Qorvo US, Inc., Greensboro, NC (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 23/367 (2006.01); H01L 23/498 (2006.01); H01L 21/3105 (2006.01); H01L 23/00 (2006.01); H01L 23/50 (2006.01); H01L 23/29 (2006.01); H01L 21/762 (2006.01); H01L 21/311 (2006.01); H01L 23/544 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3114 (2013.01); H01L 21/31058 (2013.01); H01L 21/31133 (2013.01); H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 21/76256 (2013.01); H01L 21/78 (2013.01); H01L 23/293 (2013.01); H01L 23/3135 (2013.01); H01L 23/3171 (2013.01); H01L 23/367 (2013.01); H01L 23/50 (2013.01); H01L 24/05 (2013.01); H01L 24/11 (2013.01); H01L 23/544 (2013.01); H01L 24/03 (2013.01); H01L 24/13 (2013.01); H01L 24/94 (2013.01); H01L 2224/02126 (2013.01); H01L 2224/02373 (2013.01); H01L 2224/03002 (2013.01); H01L 2224/0391 (2013.01); H01L 2224/03334 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05008 (2013.01); H01L 2224/05082 (2013.01); H01L 2224/05567 (2013.01); H01L 2224/05569 (2013.01); H01L 2224/05573 (2013.01); H01L 2224/05639 (2013.01); H01L 2224/05644 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/13017 (2013.01); H01L 2224/13022 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/13082 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/94 (2013.01); H01L 2924/2064 (2013.01); H01L 2924/20641 (2013.01); H01L 2924/20642 (2013.01); H01L 2924/20643 (2013.01);
Abstract

The present disclosure relates to a wafer-level packaging process. According to an exemplary process, a precursor wafer that includes a device layer with a number of input/output (I/O) contacts, a number of bump structures over the device layer, the stop layer underneath the device layer, and a silicon handle layer underneath the stop layer is provided. Herein, each bump structure is electronically coupled to a corresponding I/O contact. A first mold compound is then applied over the device layer to encapsulate each bump structure. Next, the silicon handle layer is removed substantially. A second mold compound is applied to an exposed surface from which the silicon handle layer was removed. Finally, the first mold compound is thinned down to expose a portion of each bump structure.


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