The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 26, 2019
Filed:
Apr. 24, 2018
The United States of America, As Represented BY the Secretary of the Navy, Arlington, VA (US);
Michael Haddon, Ridgecrest, CA (US);
Jonathan Duncan, Ridgecrest, CA (US);
The United States of America, as Represented by the Secretary of the Navy, Washington, DC (US);
Abstract
A memory check ASIC for fuzes and safety and arming (S&A) devices. The memory check ASIC may comprise: an ASIC, data line, clock line, shutdown line, and reset line. The ASIC may operatively couple to a microcontroller having a flash-based memory and may comprise: a digital logic for verifying a calculated checksum based on contents of the flash-based memory. A clock signal along with the calculated checksum may be transmitted to the ASIC via the clock line and data line, respectively. A shutdown signal may be transmitted from the ASIC to the microcontroller via the shutdown line in response to the verification of the calculated checksum by the digital logic. A reset signal may synchronize sampling of the calculated checksum and may be latched by flip-flop circuits of the digital logic for a predetermined number of clock cycles.