Page-level reference voltage parameterization for solid statesolid state storage devices

Abstract

Page-level reference voltage parameterization techniques are provided for solid state memory devices. A method comprises obtaining a bit error count for a plurality of page numbers across a plurality of blocks of a solid state memory device; determining a substantially optimal reference voltage for each page number that substantially minimizes a corresponding bit error count; collecting, for each reference voltage, page numbers and corresponding substantially optimal reference voltages; and determining, for each reference voltage, a non-linear function that substantially fits a distribution of the collected page numbers and corresponding substantially optimal reference voltages, wherein a given page having a given page number is read using a plurality of parameters of the non-linear function to generate the substantially optimal reference voltage for the given page number. At least one additional page is optionally read using a mean value for the substantially optimal reference voltage for the page number of the additional page.