The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2019

Filed:

Oct. 17, 2017
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Chongqing Boe Optoelectronics Technology Co., Ltd., Chongqing, CN;

Inventors:

Shuai Chen, Beijing, CN;

Zhi Zhang, Beijing, CN;

Cheng Zuo, Beijing, CN;

Heecheol Kim, Beijing, CN;

Taeyup Min, Beijing, CN;

Zhihui Wang, Beijing, CN;

Xiaojun Zuo, Beijing, CN;

Xing Dong, Beijing, CN;

Wangjing Bai, Beijing, CN;

Kangpeng Dang, Beijing, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01); G09G 5/00 (2006.01); H03K 17/687 (2006.01); G09G 3/292 (2013.01);
U.S. Cl.
CPC ...
G09G 3/3655 (2013.01); G09G 3/2927 (2013.01); G09G 3/3648 (2013.01); H03K 17/6871 (2013.01); G09G 2310/0243 (2013.01); G09G 2310/0245 (2013.01); G09G 2310/063 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0247 (2013.01); G09G 2320/0257 (2013.01); G09G 2330/026 (2013.01); G09G 2330/027 (2013.01);
Abstract

The present disclosure relates to a discharging circuit and a driving method thereof, and a display device. The discharging circuit of the present disclosure includes a control circuit, a time delay circuit, a first discharging circuit and a second discharging circuit. The control circuit is configured to control potential of a control signal output terminal of the control circuit. The time delay circuit is configured to delay a switched-on time of the second discharging circuit. The first discharging circuit is configured to pull down a potential of a data signal terminal to a potential of a common voltage terminal, under control of a control signal output from the control circuit. The second discharging circuit is configured to release the potential of the common voltage terminal and the potential of the data signal terminal under the control of the time delay circuit.


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