The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2019

Filed:

Jan. 19, 2017
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Inventors:

Hidetomo Kobayashi, Kanagawa, JP;

Roh Yamamoto, Kanagawa, JP;

Kei Takahashi, Kanagawa, JP;

Assignee:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); G11C 27/02 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
G09G 3/36 (2013.01); G09G 3/3688 (2013.01); G11C 27/024 (2013.01); H01L 27/1225 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78648 (2013.01); H01L 29/78696 (2013.01); G09G 2310/0291 (2013.01); G09G 2310/0294 (2013.01);
Abstract

Objects are to provide a semiconductor device with a novel structure, to provide a semiconductor device with low power consumption, and to provide a semiconductor device with a small chip area. A digital-analog converter and a frame memory are included. The frame memory includes a sample-and-hold circuit, a correction circuit, and a source follower circuit. The sample-and-hold circuit retains the analog voltage output from the digital-analog converter. The correction circuit corrects the analog voltage retained in the sample-and-hold circuit. The source-follower circuit outputs the corrected analog voltage. The sample-and-hold-circuit, the correction circuit, and the source follower circuit each comprise a first transistor. The first transistor comprises an oxide semiconductor layer in a semiconductor layer.


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