The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 26, 2019

Filed:

Sep. 21, 2018
Applicant:

National Technology & Engineering Solutions of Sandia, Llc, Albuquerque, NM (US);

Inventors:

Matthew Marinella, Gilbert, AZ (US);

Sapan Agarwal, Dublin, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G06F 17/16 (2006.01); G11C 16/04 (2006.01); G06N 3/04 (2006.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
G06F 17/16 (2013.01); G11C 16/0408 (2013.01); G11C 16/0466 (2013.01); G06N 3/04 (2013.01); H01L 29/792 (2013.01);
Abstract

A method for programming substantially simultaneously more than one of the three-terminal memory cells that represent the values of a matrix to be multiplied by a vector is disclosed. Programming may be achieved by controlling the gate-drain voltage for more than one cell simultaneously to change each such cell's physical state and hence its effective resistance. Illustratively, the gates of each row of the cells corresponding to the matrix are coupled together and each coupled row is coupled to a respective controllable voltage source while the drains of each column of the cells of the matrix are coupled together and each coupled column is coupled to a respective controllable voltage source. The controllable voltage sources are arranged so that at the intersection of a row and a column, a cell experiences one of three conditions: increase effective resistance, decrease effective resistance, or substantially no change.


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