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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10489129 B1

PDFFull Text
Expired
Date of Patent:
Nov. 26, 2019

Filed:

Apr. 02, 2018

Layered vector architecture compatibility for cross-system portability

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Michael K. Gschwind, Chappaqua, NY (US);

Ronald I. McIntosh, Toronto, CA;

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);

Attorneys:

Steven Chiu, Esq.

Blanche E. Schiller, Esq.

Heslin Rothenberg Farley & Mesiti P.C.

Primary Examiner:

Tuan C Dao

Assistant Examiner:

William C Wood

Int. Cl.
CPC ...
G06F 8/41 (2018.01); G06F 7/76 (2006.01); G06F 9/30 (2018.01); G06F 11/36 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 8/443 (2013.01); G06F 7/76 (2013.01); G06F 7/768 (2013.01); G06F 8/41 (2013.01); G06F 8/4441 (2013.01); G06F 9/30036 (2013.01); G06F 11/3624 (2013.01); G06F 13/4013 (2013.01);
Abstract

An application that includes intrinsics defined in one architecture is to execute without change on a different architecture. Program code that depends on vector element ordering is obtained, and that program code is part of an application including one or more intrinsics. The one or more intrinsics are mapped from a first system architecture for which the application was written to a second system architecture. One or more operations of the program code are then converted from a first data layout to a second data layout. The application, including the mapped intrinsics and the converted data layout, is to be executed on a processor of the different architecture.

Find Patent Forward Citations

Gschwind, Michael. (2019). Layered vector architecture compatibility for cross-system portability (U.S. Patent No. 10489129). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10489129

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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