The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 26, 2019
Filed:
Dec. 22, 2016
Cypress Semiconductor Corporation, San Jose, CA (US);
Mark Alan McClain, San Diego, CA (US);
Willy Obereiner, San Jose, CA (US);
Rainer Hoehler, Colorado Springs, CO (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
Disclosed herein are systems, methods, and devices for user configurable wear leveling of non-volatile memory devices. Devices include a non-volatile memory including a plurality of physical memory portions, where each of the plurality of physical memory portions is configured to be mapped to a logical memory portion of a plurality of logical memory portions. Devices may also include wear leveling control circuitry configured to receive a plurality of wear leveling parameters, and further configured to determine a plurality of wear leveling characteristics based on the plurality of wear leveling parameters received, where the plurality of wear leveling characteristics identify an amount of wear leveling allowed for each of the plurality of logical memory portions.