The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2019

Filed:

Feb. 23, 2018
Applicant:

Invecas, Inc., Santa Clara, CA (US);

Inventors:

Siva Kumar Rapina, Bengaluru, IN;

Saravana Kumar Durairaj, Bengaluru, IN;

Assignee:

Invecas, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04W 4/33 (2018.01); H04L 27/156 (2006.01); H03K 5/003 (2006.01); H03K 9/08 (2006.01);
U.S. Cl.
CPC ...
H04L 27/1566 (2013.01); H03K 5/003 (2013.01); H03K 9/08 (2013.01); H04W 4/33 (2018.02);
Abstract

A receiver for demodulating a pulse width modulated ('PWM') signal, comprises: a voltage level shifter for shifting the PWM signal to predefined transistor voltage levels; a half-rate PWM decoder for receiving the shifted PWM signal; and a 2-bit-to-N-bit deserializer. The half-rate PWM decoder comprises a first decoder core, a second decoder core, a controller, and a sampler and retiming circuit. The first decoder core and the second decoder core are configured to decode alternating periods of the shifted PWM signal. The controller is coupled to the first decoder core, the second decoder core, the sampler and retiming circuit. The retiming circuit is configured to receive clock signals from the controller and to output half-rate even data from the first decoder core and half-rate odd data from the second decoder core. Outputs of the retiming circuit and an output of the controller are coupled to inputs of the deserializer.


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