The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2019

Filed:

Mar. 13, 2018
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Yi Zhuang, San Jose, CA (US);

Winson Lin, San Francisco, CA (US);

Jinyung Namkoong, San Jose, CA (US);

Hsung Jai Im, San Jose, CA (US);

Stanley Y. Chen, Cupertino, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); H04L 7/033 (2006.01); G06F 1/06 (2006.01); H03K 19/0175 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0331 (2013.01); G06F 1/06 (2013.01); H03K 19/017509 (2013.01); H04L 7/0025 (2013.01); H04L 7/0087 (2013.01); H03K 19/20 (2013.01);
Abstract

A circuit for receiving a signal in an integrated circuit is described. The circuit comprises a sampler configured to receive an input data signal, wherein the sampler generates sampled data and a recovered clock; a clock and data recovery circuit configured to receive the sampled data and the recovered clock and to generate a phase interpolator code; and a phase interpolator configured to receive the phase interpolator code; wherein the phase interpolator generates multiple phase interpolator control signals during a clock cycle based upon the phase interpolator code generated for the clock cycle.


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