The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2019

Filed:

Aug. 23, 2017
Applicant:

Nihon Dempa Kogyo Co., Ltd., Tokyo, JP;

Inventors:

Tomoya Yorita, Saitama, JP;

Shoichi Tsuchiya, Saitama, JP;

Yasuo Kitayama, Saitama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/10 (2006.01); H03L 1/02 (2006.01); G06F 1/08 (2006.01); H03K 21/10 (2006.01); H03L 7/18 (2006.01);
U.S. Cl.
CPC ...
H03L 1/027 (2013.01); G06F 1/08 (2013.01); G06F 1/10 (2013.01); H03K 21/10 (2013.01); H03L 7/18 (2013.01);
Abstract

A clock generating circuit includes a dividing unit and a distribution unit. The dividing unit divides a reference clock to generate a divided clock, and the divided clock has a frequency of 1/N times of a frequency of the reference clock, where N is an integer of two or more. The distribution unit distributes the reference clock to a first route and a second route, the first route includes an output terminal that outputs a clock with a frequency identical to the frequency of the reference clock, and the second route includes the dividing unit. The dividing unit includes one or more amplifiers, one or more dividing circuits, and a correction circuit. The correction circuit is disposed between the amplifier and the dividing circuit, and the correction circuit corrects a level of an input clock input to the dividing circuit.


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