Phase interpolator, timing generator, and semiconductor integrated circuit

Abstract

During a period in which a first signal Sand second signal Sare both set to a first level, an initializing circuit initializes a capacitor voltage. Multiple circuit units are coupled in parallel between an intermediate line and a second line. An output circuit generates an output signal Sthat changes level when the capacitor voltage crosses a predetermined threshold value V. Each circuit unit includes a resistor Rand first path arranged in series between the intermediate and second lines and a second path parallel to the first path. The first path is configured to turn on when the first signal Sis the second level and the corresponding bit of an input code is a first value. The second path is configured to turn on when the second signal Sis the second level and the corresponding bit of the input code is a second value.