The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2019

Filed:

Aug. 10, 2018
Applicant:

Integrated Device Technology, Inc., San Jose, CA (US);

Inventors:

Samet Zihir, San Diego, CA (US);

Tumay Kanar, San Diego, CA (US);

Naveen Krishna Yanduru, San Diego, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04B 7/06 (2006.01); H01Q 21/00 (2006.01); H04B 1/44 (2006.01); H03F 1/56 (2006.01); H03F 3/19 (2006.01); H03G 3/30 (2006.01); H03F 3/24 (2006.01); H03K 21/10 (2006.01); H04B 1/04 (2006.01); H04B 1/18 (2006.01); H04B 1/48 (2006.01); H01Q 1/52 (2006.01); H01Q 3/28 (2006.01); H01Q 3/36 (2006.01); H01Q 19/30 (2006.01); H01Q 21/06 (2006.01); H03F 1/02 (2006.01); H01Q 1/48 (2006.01); H01Q 1/22 (2006.01); H03H 7/48 (2006.01); H04B 1/401 (2015.01); H03F 1/32 (2006.01); H03F 3/195 (2006.01); H03F 3/45 (2006.01); H03F 3/68 (2006.01);
U.S. Cl.
CPC ...
H01Q 21/0006 (2013.01); H01Q 1/2283 (2013.01); H01Q 1/48 (2013.01); H01Q 1/523 (2013.01); H01Q 1/526 (2013.01); H01Q 3/28 (2013.01); H01Q 3/36 (2013.01); H01Q 19/30 (2013.01); H01Q 21/0025 (2013.01); H01Q 21/062 (2013.01); H01Q 21/065 (2013.01); H03F 1/0211 (2013.01); H03F 1/0261 (2013.01); H03F 1/3282 (2013.01); H03F 1/565 (2013.01); H03F 3/19 (2013.01); H03F 3/195 (2013.01); H03F 3/245 (2013.01); H03F 3/45089 (2013.01); H03F 3/45475 (2013.01); H03F 3/68 (2013.01); H03G 3/3042 (2013.01); H03H 7/487 (2013.01); H03K 21/10 (2013.01); H04B 1/0458 (2013.01); H04B 1/18 (2013.01); H04B 1/401 (2013.01); H04B 1/44 (2013.01); H04B 1/48 (2013.01); H04B 7/0617 (2013.01); H03F 2200/294 (2013.01); H03F 2200/387 (2013.01); H03F 2200/451 (2013.01);
Abstract

An apparatus includes a switching circuit and a plurality of registers. The switching circuit may be configured to generate a sequence of pulses in a plurality of control signals in response to a plurality of cycles of an enable signal. The registers may be hardwired as a plurality of subsets. Each of the subsets of the registers may be configured to (a) buffer a plurality of setting values received from a memory and (b) present the setting values from the registers to a plurality of transceiver circuits while a corresponding one of the control signals is in an active state. The transceiver circuits may be updated with the setting values from the registers within a predetermined time.


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