The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2019

Filed:

Aug. 06, 2015
Applicant:

Osram Opto Semiconductors Gmbh, Regensburg, DE;

Inventors:

Kok Eng Ng, Air Itam, MY;

Wui Chai Chew, Bayan Lepas, MY;

Choo Kean Lim, Penang, MY;

Mardiana Khalid, Balik Pulau, MY;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 33/64 (2010.01); H01L 23/373 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 25/075 (2006.01); H01L 33/62 (2010.01); H01L 33/50 (2010.01);
U.S. Cl.
CPC ...
H01L 33/647 (2013.01); H01L 21/4846 (2013.01); H01L 23/3735 (2013.01); H01L 23/49811 (2013.01); H01L 23/5386 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 24/83 (2013.01); H01L 24/85 (2013.01); H01L 24/92 (2013.01); H01L 25/0753 (2013.01); H01L 33/62 (2013.01); H01L 33/641 (2013.01); H01L 33/50 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48101 (2013.01); H01L 2224/48106 (2013.01); H01L 2224/48137 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/85801 (2013.01); H01L 2224/92247 (2013.01); H01L 2924/12041 (2013.01); H01L 2933/0066 (2013.01);
Abstract

An electronic device includes a carrier and a semiconductor chip, wherein the carrier includes a first dielectric layer and a second dielectric layer, a thermal conductivity of the first dielectric layer exceeds a thermal conductivity of the second dielectric layer, the second dielectric layer is arranged on the first dielectric layer and partially covers the first dielectric layer, the semiconductor chip is arranged on the carrier in a mounting area in which the first dielectric layer is not covered by the second dielectric layer, and the carrier includes a solder terminal for electrical contacting arranged on the second dielectric layer.


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