The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2019

Filed:

Jan. 12, 2018
Applicant:

Korea University Research and Business Foundation, Seoul, KR;

Inventors:

Sangsig Kim, Seoul, KR;

Kyoungah Cho, Seoul, KR;

Minsuk Kim, Gyeonggi-do, KR;

Yoonjoong Kim, Seoul, KR;

Sola Woo, Gyeonggi-do, KR;

Doohyeok Lim, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/118 (2006.01); G06N 3/04 (2006.01); G06N 3/06 (2006.01); G11C 11/39 (2006.01); H01L 29/749 (2006.01); H01L 27/06 (2006.01); G11C 11/54 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 27/102 (2006.01); G06N 3/063 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11807 (2013.01); G06N 3/04 (2013.01); G06N 3/06 (2013.01); G11C 11/39 (2013.01); G11C 11/54 (2013.01); H01L 21/823814 (2013.01); H01L 21/823885 (2013.01); H01L 27/0688 (2013.01); H01L 27/092 (2013.01); H01L 29/749 (2013.01); G06N 3/063 (2013.01); H01L 27/1027 (2013.01); H01L 2027/11838 (2013.01); H01L 2027/11875 (2013.01);
Abstract

A semiconductor device includes stacked transistors. Each of the transistors includes a semiconductor column including a first conductive region of first conductivity type, a second conductive region of second conductivity type, an intrinsic region disposed between the first conductive region and the second conductive region, and a barrier region of the first conductivity type disposed between the intrinsic region and the second conductive region. A gate electrode is disposed to cover the intrinsic region, and a gate insulating layer is disposed between the gate electrode and the intrinsic region.


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