The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 19, 2019
Filed:
Nov. 13, 2018
Applicant:
SK Hynix Inc., Gyeonggi-do, KR;
Inventors:
Yung Jun Kim, Seoul, KR;
Suk Goo Kim, Gyeonggi-do, KR;
Assignee:
SK hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); G11C 5/02 (2006.01); H01L 27/11565 (2017.01); H01L 27/1157 (2017.01); H01L 27/11575 (2017.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 27/11568 (2017.01); H01L 27/11573 (2017.01); G11C 7/18 (2006.01); G11C 16/04 (2006.01); G11C 16/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); G11C 5/025 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 27/1157 (2013.01); H01L 27/11565 (2013.01); H01L 27/11568 (2013.01); H01L 27/11573 (2013.01); H01L 27/11575 (2013.01); G11C 7/18 (2013.01); G11C 16/0466 (2013.01); G11C 16/06 (2013.01);
Abstract
A semiconductor memory device includes a cell array region formed on a substrate, a word line contact region, and a page buffer region coupled to the cell array region through bit lines, wherein at least one of the bit lines has a curved structure toward the word line contact region. According to an embodiment, a misalignment between a cell plug and a contact plug caused by a natural cell plug bending phenomenon may be reduced to improve operational reliability of a semiconductor memory device.