The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2019

Filed:

Nov. 23, 2015
Applicant:

Institute of Microelectronics, Chinese Academy of Sciences, Beijing, CN;

Inventor:

Tianchun Ye, Beijing, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 27/11582 (2017.01); H01L 21/306 (2006.01); H01L 21/324 (2006.01); H01L 21/28 (2006.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/02592 (2013.01); H01L 21/28282 (2013.01); H01L 21/30604 (2013.01); H01L 21/324 (2013.01); H01L 29/7926 (2013.01); H01L 21/02527 (2013.01); H01L 21/02529 (2013.01); H01L 21/02532 (2013.01); H01L 21/02538 (2013.01); H01L 21/02551 (2013.01); H01L 21/02667 (2013.01);
Abstract

A method of manufacturing a semiconductor device, comprising the steps of: forming a gate dielectric layer and a first amorphous channel layer on a substrate; thinning the first amorphous channel layer; etching the first amorphous channel layer and the gate dielectric layer until the substrate is exposed; forming a second amorphous channel layer on the first amorphous channel layer and the substrate; annealing such that the first amorphous channel layer and the second amorphous channel layer are converted into a polycrystalline channel layer; and thinning the polycrystalline channel layer. According to the method of manufacturing semiconductor device of the present invention, the grain size of the polycrystalline thin film is increased by depositing a thick amorphous film and then annealing and thinning it. An additional protective layer is used to avoid etching damage on the sidewalls, effectively reducing the interface state and damage defects of the polycrystalline channel layer, thereby enhancing the reliability of the device.


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