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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10483176 B1

PDFFull Text
Date of Patent:
Nov. 19, 2019

Filed:

Dec. 04, 2015

Semiconductor module

Applicant:

Mitsubishi Electric Corporation, Tokyo, JP;

Inventor:

Daisuke Oya, Tokyo, JP;

Assignee:

Mitsubishi Electric Corporation, Tokyo, JP;

Attorney:

Studebaker & Brackett PC

Primary Examiner:

Peniel M Gumedzoe

Int. Cl.
CPC ...
H01L 23/10 (2006.01); H01L 25/07 (2006.01); H01L 23/373 (2006.01); H01L 23/04 (2006.01); H01L 23/053 (2006.01); H01L 23/24 (2006.01); H01L 25/18 (2006.01); H01L 23/367 (2006.01);
U.S. Cl.
CPC ...
H01L 23/10 (2013.01); H01L 23/04 (2013.01); H01L 23/053 (2013.01); H01L 23/24 (2013.01); H01L 23/3735 (2013.01); H01L 25/072 (2013.01); H01L 23/367 (2013.01); H01L 25/18 (2013.01); H01L 2224/32225 (2013.01); H01L 2924/1033 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/10272 (2013.01); H01L 2924/12032 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/3511 (2013.01); H01L 2924/3512 (2013.01);
Abstract

Provided is a semiconductor module in which a case and a base plate joined together with a simple structure, the semiconductor module having high insulation strength. The semiconductor module includes the following: a base plate; at least one semiconductor chip disposed inside the base plate other than the outer periphery of the base plate and above the base plate; and a case joined to the outer periphery of the base plate with an adhesive, and containing the at least one semiconductor chip. The upper surface of the base plate is provided with a recess or a protrusion between an inner wall of the case and the at least one semiconductor chip in a plan view.

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