The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2019

Filed:

Aug. 28, 2018
Applicant:

Towerjazz Panasonic Semiconductor Co., Ltd., Uozu, Toyama, JP;

Inventors:

Yuka Inoue, Toyama, JP;

Mitsunori Fukura, Kyoto, JP;

Nobuyoshi Takahashi, Toyama, JP;

Masahiro Oda, Hyogo, JP;

Hisashi Yano, Kyoto, JP;

Yutaka Ito, Hyogo, JP;

Yasunori Morinaga, Toyama, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/3205 (2006.01); H01L 23/12 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3205 (2013.01); H01L 21/76802 (2013.01); H01L 21/76808 (2013.01); H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 21/76898 (2013.01); H01L 23/12 (2013.01); H01L 23/481 (2013.01); H01L 23/522 (2013.01);
Abstract

A semiconductor device includes a first interlayer film formed on an upper surface of a substrate, a first metal wiring line, a second interlayer film, a second metal wiring line, a first via electrically connecting the first metal wiring line and the second metal wiring line, a landing pad embedded in an upper portion of the first interlayer film and penetrating the second interlayer film, and a second via penetrating the substrate and the first interlayer film from a back side of the substrate and connected to the landing pad. The lower surface position of the landing pad is different from that of the first metal wiring line.


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