The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2019

Filed:

May. 11, 2017
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventor:

Masaaki Shinohara, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 27/11568 (2017.01); H01L 27/11573 (2017.01); H01L 27/11575 (2017.01); H01L 27/1157 (2017.01); H01L 21/321 (2006.01); H01L 29/423 (2006.01); H01L 29/792 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28282 (2013.01); H01L 21/3212 (2013.01); H01L 27/1157 (2013.01); H01L 27/11568 (2013.01); H01L 27/11573 (2013.01); H01L 27/11575 (2013.01); H01L 29/42344 (2013.01); H01L 29/66537 (2013.01); H01L 29/66545 (2013.01); H01L 29/66833 (2013.01); H01L 29/792 (2013.01);
Abstract

Provided is a semiconductor device having improved performance. In a semiconductor substrate located in a memory cell region, a memory cell of a nonvolatile memory is formed while, in the semiconductor substrate located in a peripheral circuit region, a MISFET is formed. At this time, over the semiconductor substrate located in the memory cell region, a control gate electrode and a memory gate electrode each for the memory cell are formed first. Then, an insulating film is formed so as to cover the control gate electrode and the memory gate electrode. Subsequently, the upper surface of the insulating film is polished to be planarized. Thereafter, a conductive film for the gate electrode of the MISFET is formed and then patterned to form a gate electrode or a dummy gate electrode for the MISFET in the peripheral circuit region.


Find Patent Forward Citations

Shinohara, Masaaki. (2019). Method of manufacturing semiconductor device having a nonvolatile memory and a misfet (U.S. Patent No. 10483114). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10483114

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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