The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 19, 2019

Filed:

Mar. 05, 2018
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Kei Shiraishi, Kawasaki Kanagawa, JP;

Masaru Koyanagi, Ota Tokyo, JP;

Mikihiko Ito, Ota Tokyo, JP;

Yasuhiro Hirashima, Kawasaki Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/14 (2006.01); G11C 16/22 (2006.01); H02H 9/04 (2006.01); G11C 7/10 (2006.01); G11C 16/30 (2006.01); G11C 16/26 (2006.01); G11C 16/10 (2006.01);
U.S. Cl.
CPC ...
G11C 16/22 (2013.01); G11C 5/143 (2013.01); G11C 7/109 (2013.01); G11C 7/1078 (2013.01); G11C 16/30 (2013.01); H02H 9/046 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01);
Abstract

A semiconductor memory device includes a first transistor including a first end connected to a first pad and a second end connected to a first node, a second transistor including a first end connected to a second pad and a second end connected to the first node, a third transistor including a first end connected to the second pad, a second end connected to the first node, and a gate connected to a second node and having a size different from that of the second transistor, a fourth transistor including a first end connected to the first pad, a second end connected to the second node, and a gate connected to the first node, and a fifth transistor including a first end connected to the second pad, a second end connected to the second node, and a gate connected to the first node.


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