The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 19, 2019
Filed:
Sep. 01, 2017
Applicant:
Cirrus Logic International Semiconductor Ltd., Edinburgh, GB;
Inventors:
Khosrow Lashkari, Palo Alto, CA (US);
Justin Allen, Mesa, AZ (US);
Assignee:
Cirrus Logic, Inc., Austin, TX (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04B 3/23 (2006.01); H04M 9/08 (2006.01); G10L 15/22 (2006.01); G10K 11/178 (2006.01); G10L 21/0232 (2013.01); G10L 25/21 (2013.01); H04R 3/04 (2006.01); G10L 21/0208 (2013.01); G10L 25/51 (2013.01); G10L 21/0216 (2013.01);
U.S. Cl.
CPC ...
G10L 21/0232 (2013.01); G10L 21/0208 (2013.01); G10L 25/21 (2013.01); H04B 3/23 (2013.01); H04M 9/082 (2013.01); H04R 3/04 (2013.01); G10L 25/51 (2013.01); G10L 2021/02082 (2013.01); G10L 2021/02163 (2013.01);
Abstract
Step size can be used to slow or freeze the adaptive filter to improve AEC system performance, such as during double talk events. An AEC control system may be used to adjust the step size based on an echo-to-disturbance energy ratio (EDER). The algorithm adjusts the step size to lower the adaptation rate when the EDER is small (or the combination of the near signal and noise is large compared to the echo) and raise the adaptation rate when the EDER is large (echo is large compared to a combination of near signal and noise).